For high-speed analog/digital conversion, generally a parallel-type A/D converter (hereinafter also referred to as “ADC”) is often used. In the case of an n-bit parallel-type ADC, (2n-1) number of voltage comparators are disposed in parallel, and a comparison reference voltage is given to each voltage comparator. Each voltage comparator compares the given comparison reference voltage with an analog input signal, and transmits the comparison result to an encoder, and the encoder finally converts it into a digital value.
The voltage comparator is generally divided into a preamplifier unit amplifying an input and a latch unit judging a value of ‘1’ or ‘0’ at last. The comparison reference voltage and the analog input signal are amplified by the preamplifier unit to a level that can be judged by the latch unit in a latter stage, so as to achieve precision.
However, in the parallel-type ADC, the number of voltage comparators increases exponentially when it is tried to raise the resolution, which presents a problem that enlargement of circuit scale, increase in power consumption, and increase in input capacity of an analog signal input terminal become obvious.
Further, on the other hand, to realize an analog circuit, countermeasures for manufacturing dispersion of elements in manufacturing processes of semiconductors and for fluctuation of characteristics of elements depending on an ambient temperature when operating are significant problems.
Particularly, the evolution (miniaturization) of CMOS processes has brought about increase in integration and speed due to miniaturization, and reduction of power consumption by lowering power supply voltage, which are generally called “scaling effects” in digital circuits. On the other hand, in analog circuits, problems have become obvious such as reduction in analog signal dynamic range accompanying lowering of power supply voltage, increase in element characteristic dispersion accompanying miniaturization, temperature variation due to mixing with large-scale digital circuits, and the like.
The reduction in analog signal dynamic range has direct influence on signal accuracy, which has lead to increase in element size for realizing high accuracy of internal elements. Furthermore, this causes increase in parasitic capacitance and consequently hinders realization of high speed.
Furthermore, even when the dynamic range is reduced, the noise level generated by heat, which is called kT/C noise, does not change. For reducing its influence, it may be necessary to increase C (capacitance value). However, this causes increase in load, which is a factor of hindering realization of high speed.
Conventionally, a high-voltage element may be used for avoiding the reduction in dynamic range, but it is disadvantageous in terms of performance and cost because the “scaling effects” cannot be utilized. Further, using relatively larger elements (for example, increasing a channel length for a transistor) for the purpose of improving characteristic dispersion of elements is a general method, but it units the similar as the increase in element size for realizing high accuracy of internal elements and is disadvantageous for realizing high speed.
As one of methods for controlling characteristic dispersion of elements, there is calibration. By setting a calibration period, many of conventional techniques perform the calibration while halting a normal operation for a given period (see Non-Patent Documents 1 to 3).
However, application of this method is limited since the normal operation is halted during the calibration period. On the other hand, there is reported a method of performing the calibration in the background (see Non-Patent Document 4).
According to this method, it is not required to set a special calibration period, so its application is not limited. However, it has a problem of increasing the number of elements because it involves a full parallel structure. Particularly, an input unit is connected in parallel when seen from a signal input terminal, which increases the load and is disadvantageous for achieving high speed.
Further, a units for interpolating an analog signal is effective for solving problems as described above, and many such units are reported (see Non-Patent Documents 5, 6). Further, a technique combining interpolation of an analog signal and the calibration in the background is also suggested (see Patent Document 1).
However, in the conventional calibration, there are two technical problems as follows. It may be necessary to correct an offset, common mode, and gain for performing interpolation accurately, but correction of only the offset is possible and the gain cannot be corrected. Moreover, a comparator with redundancy, such that a comparator of the main series performs a conversion operation as a substitute during calibration, is at a separated position from the comparator of the main series. Thus, it is not possible to retain continuity of power supply conditions, analog signal wirings, clock signal wirings, and so on. This becomes a problem in a high speed operation. A precise operation cannot be performed due to inversion of continuous relationship or sequence of signals and power supply.
As described above, in the conventional interpolation method and calibration method, precise correction of interpolation points is not possible. Therefore, for obtaining given accuracy, one is compelled to obey a conventional design method for suppressing errors of interpolation points, that is, setting to an element size by which relative accuracy can be secured. This conventional design method cannot benefit from the “scaling effects” and has been a constraint in the aspect of performance. Further, the method described in Patent Document 1 causes inversion of the order of arrangement, and thus has a problem of dynamic characteristics.
Patent Document 1: Japanese Laid-open Patent Publication No. 2002-33663
Patent Document 2: Japanese Laid-open Patent Publication No. 2003-218698
Patent Document 3: Japanese Laid-open Patent Publication No. 2003-283335
Non-Patent Document 1: Yuko Tamba, Kazuo Yamakido; A CMOS 6b 500 MSample/s ADC for a hard disk drive read channel, IEEE International Solid-State Circuits Conference, vol. XLII, pp. 324-325, February 1999
Non-Patent Document 2: Joe Spalding, Declan Dalton; A 200Msample/s 6b flash ADC in 0.6 μm CMOS, IEEE International Solid-State Circuits Conference, vol. XXXIX, pp. 320-321, February 1996.
Non-Patent Document 3: Iuri Mehr, Declan Dalton; A 500-Msample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications, IEEE Journal of Solid-State Circuits, vol. 34, pp. 912-920, July 1999.
Non-Patent Document 4: Sanroku Tsukamoto, Ian Dedic, Toshiaki Endo, Kazu-yoshi Kikuta, Kunihiko Goto, Osamu Kobayashi; A CMOS 6-b, 200 Msample/s, 3 V-supply A/D converter for a PRML read channel LSI, IEEE Journal of Solid-State Circuits, vol. 31, pp. 1831-1836, November 1996.
Non-Patent Document 5: M. Steyaert, R. Roovers, J. Craninckx; A 100 MHz 8 bit CMOS interpolating A/D converter, 1993 IEEE Custom Integrated Circuits Conference, May 1993.
Non-Patent Document 6: Hiroshi Kimura, Akira Matsuzawa, Takashi Nakamura, Shigeki Sawada; A 10-b 300-MHz interpolated-parallel A/D converter, IEEE Journal of Solid-State Circuits, vol. 28, pp. 438-446, April 1993.